Sandisk completed its first high-bandwidth flash (HBF) memory-chip tape-out in fiscal Q1; samples are planned for 2027.

A Telegram summary of Sandisk Chairman and CEO David Goeckeler’s remarks reports the first successful high-bandwidth flash memory-chip tape-out in fiscal Q1 2027. Sample delivery is planned for calendar 2027; the reported milestone is not a commercial shipment or volume-production announcement.

Sandisk describes HBF as a complement to high-bandwidth memory, or HBM, bringing NAND-scale capacity closer to processors. The stated design objectives include supporting larger models, longer context windows, and growing key-value caches, which the company described as working memory for inference workloads.

The same update outlines Sandisk’s broader NAND roadmap: BiCS 8 is the current production foundation and uses a CMOS-directly-bonded-to-array architecture, while BiCS 9 combines a mature memory array with next-generation CMOS circuitry to improve interface performance. BiCS 10 advances both triple-level-cell and quad-level-cell flash, with a 2-terabit quad-level-cell die and reported doubling of read/write bandwidth.

Management also forecast that key-value caches would account for approximately one-third of the AI data-center flash market by the end of the decade. That is a market forecast, separate from the completed HBF tape-out; the supplied summary does not disclose HBF chip capacity, bandwidth, power consumption, or sample quantities.