University of California, Santa Cruz researchers published work on backside clock meshes that reduce skew and power in 2-nanometer nanosheets.

Semiconductor Engineering covered a technical paper by University of California, Santa Cruz researchers titled “Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology.” Here, GAAFET means gate-all-around field-effect transistor, and BSPDN means backside power-delivery network.

The supplied abstract explains that clock meshes are used in high-performance very-large-scale integration (VLSI) designs to minimize clock skew and tolerate on-chip variation. It also identifies their routing cost: conventional meshes consume scarce resources on premium metal layers.

The article headline reports reductions in skew and power using backside clock meshes in the 2-nanometer nanosheet context. The excerpt does not provide percentage improvements, absolute power savings, timing measurements, or evidence of a commercial chip deployment.