Researchers published RAPID, a row-parallel arithmetic-processing architecture for dynamic random-access memory, reducing data-reorganization overhead in in-memory computing.

Researchers from Syracuse University, Friedrich-Alexander University Erlangen-Nuremberg (Friedrich-Alexander-Universität Erlangen-Nürnberg), and TU Dresden published “RAPID: Row-Parallel Arithmetic Processing in DRAM.” DRAM means dynamic random-access memory; RAPID is the research architecture, not a separately announced commercial memory product.

The supplied abstract describes processing-using-memory (PUM) architectures as performing computation directly within DRAM to reduce costly movement between memory and processors. It explains that existing DRAM-PUM designs face constraints because charge-sharing operations are confined to individual bitlines.

Those constraints lead existing architectures to reorganize data into column-oriented, bit-serial layouts, the overhead addressed by the reported row-parallel approach. The source headline reports reduced data-reorganization overhead, but the excerpt does not include speedup, energy savings, area overhead, or benchmark results.