Silicon-infrastructure developer SignatureIP launched MesoLink, a bridge for PCIe and Compute Express Link validation that preserves device-native generation, lane width, and timing.

SignatureIP introduced MesoLink, described as a mesochronous connectivity bridge intellectual-property core. Its stated role is validation of Peripheral Component Interconnect Express (PCIe) and Compute Express Link (CXL) devices.

The device under test retains its native interface generation, lane width, and timing. On the field-programmable gate array (FPGA) side, the serializer/deserializer, or SerDes, operates at full rate.

The announcement positions MesoLink for plug-and-play prototyping and emulation. The excerpt does not specify supported PCIe or CXL versions, numerical transfer rates, validation-time savings, or licensing terms.