University of Alberta researchers introduced PPAPlace, optimizing placements against post-route performance, power, and area rather than wirelength alone.

University of Alberta researchers published a technical paper titled “PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization.” PPA refers to the post-route performance, power and area characteristics of a chip design.

The researchers focused on macro placement, which materially affects those post-route results. They noted that most existing placement approaches use half-perimeter wirelength (HPWL) as their primary optimization objective.

The paper’s abstract states that recent benchmarking found a near-zero correlation between HPWL and post-route timing metrics. PPAPlace instead uses differentiable cross-stage objectives designed to connect placement optimization more directly with post-route PPA outcomes.