Google and Delft University of Technology demonstrated hardware enabling system-level failure analysis of 3D integrated-circuit packages with stacked DRAM.

Researchers from Google and Delft University of Technology published a technical paper titled “Innovative FA Hardware Solution to Enable System-Level Debug of 3D ICs.” FA refers to failure analysis, while 3D ICs are three-dimensional integrated circuits.

The work presents new failure-analysis hardware and a sample-preparation solution for system-level analysis. It targets mobile system-on-chip package-on-package devices in which dynamic random-access memory, or DRAM, is stacked above the system-on-chip.

The system-level scope distinguishes the work from analysis limited to an isolated die or component. The supplied abstract did not provide performance figures, supported package dimensions, commercial availability, or a production deployment schedule.