Memory manufacturer CXMT unveiled a 4F² DRAM architecture using Vertical Surrounded Gate transistors and expects new DDR5 server-memory modules by year-end.

The underlying technical presentation occurred on October 10. The supplied October 14 report says CXMT president Dr. Cao Kanyu presented progress in dynamic random-access memory, or DRAM, devices, 4F² architecture, and hybrid bonding at the fourth Integrated Chips and Chiplets Conference. The report therefore concerns newly covered details of an earlier presentation, rather than an October 14 product shipment.

The architecture reduces the stated memory-cell footprint relative to the mainstream 6F² design. In the report’s explanation, a 4F² cell occupies four times the square of the minimum feature size. It says this allows more transistors per unit area and higher storage density.

The central device innovation is CXMT’s self-developed Vertical Surrounded Gate transistor. The report identifies this transistor design, abbreviated VSG, as the key change within the DRAM storage array. Hybrid bonding is also listed among the areas of progress, but the source does not provide a detailed implementation specification.

The server-memory product remains an expected year-end release. CXMT said it expected a new generation of DDR5 registered dual in-line memory modules, or RDIMMs, incorporating new technologies by the end of 2026. The source gives no module capacities, speeds, production yields, or confirmed customer shipments.