Purdue University researchers introduced DRC-Aid, an agentic framework automating local chip-layout design-rule repairs through verification-in-the-loop search while preserving layout equivalence.

DRC-Aid applies an agentic approach to local design-rule correction. Purdue University researchers describe it as a closed-loop framework that formulates design-rule checking (DRC) repair as verification-in-the-loop search. The paper is titled “DRC-Aid: Design-Rule Correction via Agentic Framework utilizing Inference-Time Large Language Models.”

The disclosed method includes a deterministic Rule Engine. The abstract says this engine constrains the combinatorial geometric repair space and begins describing how it converts information reported by a physical-verification tool. The supplied excerpt ends before completing that description, so the precise conversion process is not available.

Layout equivalence is a stated property of the reported approach. Semiconductor Engineering’s headline describes automated design-rule repair while preserving layout equivalence, and the abstract identifies the task as local repair. The provided material does not include repair-success rates, runtime measurements, comparison baselines, supported process nodes, or evidence of production deployment.