National University of Singapore researchers presented CHIPSMORE, an inference-accelerator design combining compute-in-interconnect and compute-in-memory for base-model and low-rank-adaptation workloads.

CHIPSMORE addresses multiple modes and requests in large language model inference. Semiconductor Engineering reports a National University of Singapore technical paper titled “CHIPSMORE: Compute-in-Interconnect and -Memory Chiplets for Multi-Mode Multi-Request LLM Inference Acceleration.” The supplied abstract describes an accelerator for large language model (LLM) inference under diverse workloads.

The architectural feature is the integration of two computing approaches. CHIPSMORE combines compute-in-interconnect with compute-in-memory (CIM). The abstract explicitly identifies support for both base-mode inference and low-rank adaptation (LoRA) inference.

The available evidence is a research-paper summary, not a commercial product disclosure. The article title identifies heterogeneous memory chiplets, but the supplied excerpt stops before further implementation details. It provides no numerical throughput, latency, energy-efficiency result, fabrication node or commercial availability information.