Researchers from NVIDIA and Duke University published SCALE, a self-supervised method targeting place-and-route design-rule violations at sub-2-nanometer nodes.

Researchers from NVIDIA and Duke University published a technical paper titled “SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes.” P&R refers to place-and-route, while DRV means design-rule violation.

The work focuses on local place-and-route design-rule-violation fixing as semiconductor manufacturing advances toward sub-2-nanometer process nodes. The researchers identify complex rule interactions, dense multi-layer routing geometries, and foundry-specific constraints as limitations affecting this task.

SCALE is described as a self-supervised and constraint-aware layout-generation method. Its target is local correction of design-rule violations in advanced-node physical layouts, rather than model training, inference serving, or manufacturing equipment operation.

The publication is a research paper rather than a disclosed commercial electronic-design-automation product or production deployment. The supplied source does not provide commercial availability, customer adoption, or manufacturing-yield results.